In 12 hours, an AI system designed a complete processor that could run code. Not a simulation. Not a concept. A real chip design, complete and ready to send to a semiconductor foundry.
Verkor.io's Design Conductor produced the VerCore RISC-V CPU from a 219-word specification. The resulting design hit 1.5 gigahertz—performance comparable to laptop processors from 2011. Suresh Krishna, cofounder at Verkor.io, frames the achievement as fundamentally different from incremental AI assistance in chip design. "What we learned is that the better approach is to let the AI agent solve the whole problem," he says.
Design Conductor is not itself an AI model. It is a harness—a software framework that orchestrates large language models through the same structured workflow a team of human chip architects follows. Starting from a natural-language specification, the system analyzes requirements, writes and debugs register-transfer level code, then iterates through subtasks including power delivery, signal timing, and physical layout. It outputs a GDSII file, the industry-standard format that semiconductor foundries accept for manufacturing.
This is the key distinction. Synopsys and Cadence, the dominant forces in chip design software, have introduced AI agents into their tools. But these agents automate specific subtasks—timing analysis, power optimization—while human architects remain the orchestrators. Design Conductor removes that coordinator entirely. Ravi Krishna, founding engineer at Verkor.io, describes the workflow as "mirrored after the traditional process a human engineer might use." The system checks each iteration against the original specification, calling external tools only when necessary.
The 12-hour design time raises obvious questions about parallelism. Ravi Krishna notes that not all tasks in chip design parallelize easily. But the trajectory matters more than the current number. "I remember that around the middle of last year, we tried to build a floating-point multiplier with the models of that time. It was slightly beyond what they could do," he says. By April 2026, the same approach produced a complete RISC-V core.
The performance level—roughly equivalent to 2011-era laptop CPUs—reflects the genuine complexity of modern processor design rather than any fundamental limitation of the approach. Producing a design at 1.5GHz that could actually boot and execute instructions represents a credible working processor, not a toy demonstration.
What this suggests is a narrowing path from specification to silicon. The traditional CPU design cycle takes 18 months or more for complex parts; AI-directed design could compress that to days. The bottleneck shifts from human engineering hours to AI model capability and the quality of the design harness. That is where competitive advantage would concentrate—not in hiring hundreds of RTL engineers, but in building the AI infrastructure and specification expertise to direct the agent effectively.
The caveats are real. Verkor's results have not been independently verified. Modern flagship processors operate at 3-4GHz with complex out-of-order execution pipelines and massive cache hierarchies; matching that performance remains far beyond current AI capabilities. Physical constraints—thermal management, process variation, manufacturing yield—emerge only during actual fabrication, not from GDSII simulations.
Still, this marks a threshold. A complete processor, generated from a brief natural-language description, by an autonomous AI agent. Not a benchmark. Not a fragment. A design you could send to TSMC. That capability did not exist two years ago.