Twenty-five times faster. That is how quickly Lunsin's AI system processes chip protocol documentation compared to human engineers, according to Chinese tech publication QbitAI. For semiconductor design teams, this is not a marginal improvement—it is the difference between a weeks-long documentation review and one that completes before lunch.
Chip protocol documentation is dense, technical, and voluminous. Engineers must parse hundreds of pages covering interfaces, timing constraints, voltage thresholds, and error handling rules. Every specification must be understood correctly before verification code can be written. Mistakes at this stage are catastrophic.
The problem is what chip designers call respin-level bugs. These are specification errors caught so late that teams must rebuild physical masks—a process costing $10 million to $50 million and adding three to six months to project timelines. Some companies have lost an entire fiscal year's profit on a single respin. Catching these bugs earlier would save both money and time.
Lunsin's system does not just read faster. It outputs usable verification code directly from the documentation it processes. Engineers feed in chip specifications and receive working test vectors and compliance checks without manual translation. The AI also flags inconsistencies and missing requirements—potential respin-level errors hidden in the documentation itself.
Traditional EDA vendors have offered AI-assisted tools for layout optimization and timing analysis. But documentation processing has remained stubbornly manual. Lunsin takes a different approach: instead of helping engineers implement designs faster, it helps them understand what to build correctly in the first place.
The distinction matters. Layout and timing tools improve the downstream phases of chip development. Documentation intelligence prevents errors upstream, before millions of dollars are committed to silicon. One reduces manufacturing costs. The other prevents the catastrophic waste that defines a failed tapeout.
For Chinese semiconductor teams facing tightening supply chains and accelerating design cycles, this represents a new way to think about EDA workflows. If Lunsin's claims hold under scrutiny, the tool could shift where design teams allocate their most expensive resource: engineering time.
QbitAI reports that Lunsin is actively demonstrating the system to design houses. Independent verification of bug detection accuracy and code output quality has not yet been published. The broader EDA industry is watching closely. If one company can reliably catch specification errors before physical design begins, every tapeout budget recalculates.